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ISL54503
Data Sheet August 29, 2007 FN6551.1
+1.8V to +5.5V, 2.5, Single SPDT Analog Switch
The Intersil ISL54503 device is a low ON-resistance, low voltage, bidirectional, single pole/double throw (SPDT) analog switch designed to operate from a single +1.8V to +5.5V supply. Targeted applications include battery powered equipment that benefit from low ON-resistance (2.5) and fast switching speeds (tON = 25ns, tOFF = 15ns). The digital logic input is 1.8V CMOS compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL54503 is offered in the 6 Ld 1.2mmx1.0mmx0.4mm pitch TDFN package, alleviating board space limitations. The ISL54503 is a committed SPDT that consist of one normally open (NO) and one normally closed (NC) switch. This configuration can also be used as a 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE ISL54503 Number of Switches SW 1.8V rON 1.8V tON/tOFF 3V rON 3V tON/tOFF 5V rON 5V tON/tOFF Package 1 SPDT or 2-1 MUX 6 65ns/40ns 3 30ns/20ns 2.5 25ns/15ns 6 Ld TDFN
Features
* ON-resistance (rON) - VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 - VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 - VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 * rON matching between channels . . . . . . . . . . . . . . . . . . .3m * rON flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0.6 * Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V * Fast switching action (+4.5V Supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns * Guaranteed break-before-make * ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV * 1.8V CMOS logic compatible (+3V supply) * Available in 6 Ld TDFN package * Pb-free available (RoHS compliant)
Applications
* Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops * Portable Test and Measurement * Medical Equipment * Audio and video switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54503 Ordering Information
PART NUMBER (Note) ISL54503IRUZ-T* 3 PART MARKING TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-Free) PKG. DWG. #
6 Ld TDFN (Tape and Reel) L6.1.2x1.0A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
(Note 1) ISL54503 (6 LD TDFN) TOP VIEW
NO GND NC 1 2 3 6 5 4 IN V+ COM
Pin Descriptions
NAME V+ GND IN COM NO NC PIN 5 2 6 4 1 3 FUNCTION System Power Supply Input (+1.8V to +5.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
LOGIC 0 1 NOTE: PIN NC ON OFF PIN NO OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
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ISL54503
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1400V
Thermal Information
Thermal Resistance (Typical, Notes 3, 4) JA (C/W) JC (C/W) 6 Ld TDFN Package . . . . . . . . . . . . . 239.2 111.6 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+ VIN (Digital Logic Input Voltage (IN) . . . . . . . . . . . . . . . . . 0V to V+ Temperature Range ISL54503IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 5), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 6, 7) TYP MAX (Notes 6, 7) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 9, See Figure 5) 25 Full 25 Full 25 Full 25 Full V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V, or Floating 25 Full
0 -25 -150 -30 -300
2.2 0.003 0.6 1.5 2.8 -
V+ 2.5 3 0.1 0.15 0.65 0.7 25 150 30 300
V nA nA nA nA
rON Matching Between Channels, V+ = 4.5V, ICOM = 100mA, VNO or VNC = 2.5V rON (Note 9) rON Flatness, rFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1, Note 9) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1, Note 9) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 8, 9) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V
25 Full 25 Full Full 25 25 25 25 25 25
-
25 25 15 16 15 24 70 0.15 0.014 250 7
-
ns ns ns ns ns pC dB % % MHz pF
Break-Before-Make Time Delay, tD V+ = 5.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 3, Note 9) Charge Injection, Q OFF Isolation Total Harmonic Distortion Total Harmonic Distortion -3dB Bandwidth NO or NC OFF Capacitance, COFF VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VP-P (See Figure 4) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 RL = 50 V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
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ISL54503
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 5), Unless Otherwise Specified. (Continued) TEST CONDITIONS V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) TEMP (C) 25 MIN (Notes 6, 7) TYP 18 MAX (Notes 6, 7) UNITS pF
PARAMETER COM ON Capacitance, CCOM(ON) Power Supply Range Positive Supply Current, I+
POWER SUPPLY CHARACTERISTICS Full V+ = 5.5V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full Full Full 2.4 -0.1 0.053 0.8 0.1 V V A 1.65 0.028 1.1 5.5 0.1 2.5 V A A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (Notes 6, 7) TYP MAX (Notes 6, 7) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 9, See Figure 5) 25 Full 25 Full 25 Full
0 -
3.3 0.006 1 -
V+ 3.5 4.5 0.15 0.2 1.1 1.2
V
rON Matching Between Channels, V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V rON (Note 9) rON Flatness, rFLAT(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 9) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 9) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 8, 9)
25 Full 25 Full Full 25 25 25 25 25 25 25
-
30 30 20 20 18 16 70 0.36 0.03 250 6 18
-
ns ns ns ns ns pC dB % % MHz pF pF
Break-Before-Make Time Delay, tD V+ = 3.0V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 9) Charge Injection, Q OFF Isolation Total Harmonic Distortion Total Harmonic Distortion -3dB Bandwidth NO or NC OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) Positive Supply Current, I+ VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VP-P (See Figure 4) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 Signal = 0dBm, RL = 50 f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS V+ = 3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full Full Full 1.4 -0.1 0.058 0.5 0.1 V V A 0.013 0.7 A A
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Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (Notes 6, 7) TYP MAX (Notes 6, 7) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF
Full V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+, (Note 9, See Figure 5) 25 Full
0 -
6 -
V+ 6.5 7
V
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 9) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 9)
25 Full 25 Full Full 25
-
65 95 40 65 44 8.2
-
ns ns ns ns ns pC
Break-Before-Make Time Delay, tD V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 9) Charge Injection, Q VG = 0, RG = 0, CL = 1.0nF (See Figure 2)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH NOTES: 5. VIN = input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 9. Limits established by characterization and are not production tested. Full Full 1 0.4 V V
Test Circuits and Waveforms
V+ LOGIC INPUT 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT 50% tr < 20ns tf < 20ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) --------------------------R L + r ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
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FN6551.1 August 29, 2007
ISL54503 Test Circuits and Waveforms (Continued)
V+ C
SWITCH OUTPUT VOUT
VOUT
RG
NO OR NC
COM
VOUT
VINH LOGIC INPUT ON OFF VINL Q = VOUT x CL LOGIC INPUT ON VG GND IN CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V
NO VNX NC IN LOGIC INPUT GND RL 50 CL 35pF COM VOUT
SWITCH OUTPUT VOUT
90% 0V tD
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
V+ V+ C SIGNAL GENERATOR rON = V1/I1 *
NO OR NC
C
NO OR NC
VNX IN V1 IN VINL OR VINH
0V OR V+
I1 100mA
COM
ANALYZER RL
COM
GND
* I = 10mA AT V+ = 1.8V 1
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
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FN6551.1 August 29, 2007
ISL54503 Test Circuits and Waveforms (Continued)
V+ C V+ C
50
NO OR NC
COM
NO OR NC
IN IN1 0V OR V+ SIGNAL GENERATOR IMPEDANCE ANALYZER
COM
VINL OR VINH
ANALYZER RL
NC OR NO GND
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54503 is a bidirectional, single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.8V to 5.5V supply with low ON-resistance (2.5) and high speed operation (tON = 25ns, tOFF = 15ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (0.15W), low leakage currents (300nA max), and the small TDFN package. The low ON-resistance and rON flatness provide very low insertion loss and distortion to application that require signal reproduction.
V+ OPTIONAL PROTECTION RESISTOR
NO
C
100
COM
NC
IN GND
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil recommends adding a 100 resistor in series with the V+ power supply pin of the ISL54050 IC (see Figure 8). During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation, the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance.
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 9). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation.
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This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting Schottky diodes to the signal pins (as shown in Figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current.
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, the ISL54503 has a -3dB bandwidth of 250MHz (see Figure 17). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch behaves like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to output. Off isolation is the resistance of this signal feedthrough. Figure 18 details the high off isolation provided by the ISL54503. At 1MHz, off isolation is about 70dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation due to the voltage divider action of the switch OFF impedance and the load impedance.
INX VNX VCOM
GND OPTIONAL SCHOTTKY DIODE
FIGURE 9. OVERVOLTAGE PROTECTION
Leakage Considerations
ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Power-Supply Considerations
The ISL54503 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54503 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V but the part will operate with a supply below 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables starting on page 3 and the "Typical Performance Curves" starting on page 9 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (see Figure 16). At 3.6V the VIH level is about 0.95V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced.
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FN6551.1 August 29, 2007
ISL54503 Typical Performance Curves TA = 25C, Unless Otherwise Specified
4.0 3.5 3.0 2.5 rON () 2.0 1.5 V+ = 5V 1.0 0.5 0.0 0 1 2 VCOM (V) 3 4 5 0.5 V+ = 2.7V V+ = 3V rON () ICOM = 100mA 2.5 +85C 2.0 +25C 1.5 -40C 3.0
V+ = 4.5V
1.0 V+ = 4.5V ICOM = 100mA
0.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
5.0 4.5 4.0 3.5 rON () 3.0 2.5 -40C 2.0 1.5 1.0 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 +85C +25C V+ = 2.7V ICOM = 100mA
8 7 6 +85C rON () 5 4 3 2 1 +25C -40C V+ = 1.8V ICOM = 10mA
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
100 90 80 70 +25C tOFF (ns) 60 tON (ns) 50 40 +85C 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -40C
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
70 -40C 60 50 +25C 40 30 +85C 20 10 0
1.5
2.0
2.5
3.0
V+ (V)
3.5 4.0 V+ (V)
4.5
5.0
5.5
6.0
FIGURE 14. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 15. TURN-OFF TIME vs SUPPLY VOLTAGE
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ISL54503 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
1.4 0 -1 1.2 NORMALIZED GAIN (dB) -2 -3 VINH AND VINL (V) 1.0 VINH 0.8 VINL 0.6 -4 -5 -6 -7 -8 -9 -10 0.4 -11 -12 0.2 1.5 2.0 2.5 3.0 3.5 V+ (V) 4.0 4.5 5.0 5.5 -13 100k 1M 10M FREQUENCY (Hz) 100M 1G V+ = 1.8V TO 5.5V VCOM = 1VP-P
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 17. FREQUENCY RESPONSE
-20 -30 -40 -50 V+ = 1.8V TO 5.5V
25 20 15 10
-60 -70 -80 -5 -90 -100 -110 -120 1k 10k 100k 1M 10M 100M 1G -10 -15 -20 V+ = 1.8V V+ = 3.3V Q (pC) (dB) 5 0 V+ = 5V
0.0
0.5
1.0
1.5
FREQUENCY (Hz)
2.0 2.5 3.0 VCOM (V)
3.5
4.0
4.5
5.0
FIGURE 18. OFF ISOLATION
FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: PROCESS: Submicron CMOS
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FN6551.1 August 29, 2007
ISL54503 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E A B
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
PIN 1 REFERENCE 2X 0.10 C 2X 0.10 C TOP VIEW DETAIL A 0.10 C
D
SYMBOL A A1 A3 b D
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
0.15 0.95 1.15
0.20 1.00 1.20 0.40 BSC
0.25 1.05 1.25
5 -
A 7X 0.08 C A1 A3 SIDE VIEW 4X e 1 L1 3 5X L C SEATING PLANE
E e L L1 N Ne NOTES:
0.30 0.40
0.35 0.45 6 3
0.40 0.50
2 3
DETAIL B
0
-
12
4 Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6 4 b 6X 0.10 C A B 0.05 C NOTE 3
2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
0.1x45 CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255.
A1 DETAIL A
A3 DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
1.40 0.20 0.45 0.20 0.40 LAND PATTERN 10 0.30 0.35
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6551.1 August 29, 2007

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